High quality drift layer thickness scaling in vertical GaN-on-Silicon PIN diodes
Résumé
We report on high drift layer quality in vertical PIN diodes grown on silicon substrate combining low Ron = 0.35 mΩ.cm², and high critical electric field of 1.82 MV/cm. The impact of the drift region thickness on the device performances shows an excellent breakdown scaling with 640 V / 820 V for 3.5 µm / 4.5 µm drift layer thickness, favourably comparable to the state-of-the-art.
Domaines
Sciences de l'ingénieur [physics]
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Abstract-Youssef HAMDAOUI-wocsdice-exmatec2023.pdf (376.32 Ko)
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