Functional Verification Strategy for an Open-Source High-Performance L1 Data-Cache for RISC-V cores
Résumé
The verification of caches is particularly challenging, as it is necessary to ensure that the memory consistency is ensured in all conditions and modern caches contain many complex features (out of order execution, write buffer, multiple request ports) and a complex micro-architecture in order to ensure high-performance. The recently released, Open-Source High Performance L1 Data Cache (HPDCache) for the RISC-V is delivered as a highly configurable RTL model, compounding the verification challenge as correct behaviour must be ensured for all combinations of the parameters. An approach combining pseudo random constraint and directed random test within the framework of Universal Verification Methodology (UVM) is used to be able to verify HPDcache.
Domaines
Architectures Matérielles [cs.AR]
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2023-06-07-Tanuj-KHANDELWAL-poster.pdf (742.78 Ko)
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2023-06-07-Tanuj-KHANDELWAL-abstract.pdf (350.36 Ko)
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