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Communication Dans Un Congrès Année : 2022

Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology

Résumé

In this work, Integer N frequency dividers are designed in a dual loop PLL circuit which is applicable at reference frequency 40.92MHz and 400MHz and for a feedback input frequency 0.8GHz-6.3GHz with very low power consumption and small die area. A fast and energy-efficient True Single Phase Clock (TSPC) D-Flip Flops with a controlled pre-charger circuit has been explained for designing reference and feedback frequency dividers (sequentially 4-bit De-Counter and 8-bit De-Counter). The phase noise (PN) of the dividers always remains at −130dBc/Hz at 1MHz offset. The circuit was designed and implemented in 28nm FDSOI technology and the divider's maximum current consumption is 208μA at 1 V.
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Dates et versions

hal-04337331 , version 1 (12-12-2023)

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Citer

Md Sazzad Hossain, Mateus Bernardino Moreira, Francois Sandrez, Francois Rivet, Herve Lapuyade, et al.. Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology. 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), Mar 2022, Puerto Varas, Chile. pp.1-4, ⟨10.1109/LASCAS53948.2022.9789073⟩. ⟨hal-04337331⟩
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