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Article Dans Une Revue IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Année : 2023

3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs

Cédric Marchand
Alberto Bosio
Ian O’connor
Cristell Maneux

Résumé

This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat-transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit level simulations indicate a strong impact of temperature variation on functionality and figures of merits such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements
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Dates et versions

hal-04230911 , version 1 (06-10-2023)

Identifiants

Citer

Sara Mannaa, Arnaud Poittevin, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, et al.. 3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023, 9 (2), pp.116 - 123. ⟨10.1109/JXCDC.2023.3309502⟩. ⟨hal-04230911⟩
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