3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs
Abstract
This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat-transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit level simulations indicate a strong impact of temperature variation on functionality and figures of merits such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements
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