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Communication Dans Un Congrès Année : 2023

On Using Cell-Aware Methodology for SRAM Bit Cell Testing

Résumé

The shrinking of technology nodes has led to high density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This paper presents a novel approach for memory testing which relies on Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs). Consequently, using CA methodology converts memory testing from functional to structural testing. In this work, the preliminary flow of the CA-based memory testing methodology is presented. The generation of the CA model for the SRAM bit cell has been demonstrated as a case study. The generated CA model and the structural representation of the memory are used by the ATPG to test the bit cell in the presence of short and open defects. The generated test patterns are able to detect both static and dynamic faults in the bit cell with a test coverage of 100%.
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Dates et versions

hal-04164704 , version 1 (18-07-2023)

Identifiants

Citer

Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory Di Pendina, et al.. On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS 2023 - 28th IEEE European Test Symposium, May 2023, Venezia, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174118⟩. ⟨hal-04164704⟩
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