Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory - Archive ouverte HAL Access content directly
Conference Papers Year : 2022

Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory

Abstract

We consider the verification of electrical properties of circuits to identify potential violations of electrical design rules, also called Electrical Rule Checking (ERC). We present a general approach based on Satisfiability Modulo Theory (SMT) to verify that these errors cannot occur in a given circuit. We claim that our approach is scalable and more precise than existing analyses, like voltage propagation. We applied these techniques to a specific type of errors, the missing level shifters. On an industrial casestudy, our technique is able to flag 31% of the warnings raised by the voltage propagation analysis as being false alarms.
Fichier principal
Vignette du fichier
date2023.pdf (109.31 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

hal-04007446 , version 1 (28-02-2023)

Identifiers

Cite

Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, M. Khosravian G., Matthieu Moy, et al.. Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. DATE 2023 - Design, Automation and Test in Europe Conference, Apr 2023, Anvers (Antwerpen), Belgium. pp.1-2, ⟨10.23919/DATE56975.2023.10137147⟩. ⟨hal-04007446⟩
153 View
257 Download

Altmetric

Share

Gmail Mastodon Facebook X LinkedIn More