A high-resolution clock phase shifter circuitry for ALTIROC - Archive ouverte HAL
Communication Dans Un Congrès Année : 2023

A high-resolution clock phase shifter circuitry for ALTIROC

X. Huang
  • Fonction : Auteur
D. Gong
  • Fonction : Auteur
C. Liu
  • Fonction : Auteur
T. Liu
  • Fonction : Auteur
J. Ye
  • Fonction : Auteur
L. Zhang
  • Fonction : Auteur

Résumé

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

Dates et versions

hal-03991909 , version 1 (16-02-2023)

Identifiants

Citer

X. Huang, C. de La Taille, D. Gong, C. Liu, T. Liu, et al.. A high-resolution clock phase shifter circuitry for ALTIROC. Topical Workshop on Electronics for Particle Physics, Sep 2022, Bergen, Norway. pp.C01057, ⟨10.1088/1748-0221/18/01/C01057⟩. ⟨hal-03991909⟩
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