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Proceedings/Recueil Des Communications Année : 2005

Hardware implementation of a conceptual decoder for real time analysis of MPEG-2 DVB-T stream

Michael Janiaut
  • Fonction : Auteur
Camel Tanougast
Christian Mannino
  • Fonction : Auteur
Hassan Rabah
Yves Berviller
Serge Weber

Résumé

To standardise the decoding process of system streams, MPEG defines a hypothetical decoder structure known as Transport stream System Target Decoder (T-STD). T-STD is defined for the purpose of providing formalism for definition of timings and buffering relationships at the system decoders. This conceptual model is only used to define the timing terms precisely and to model the decoding process during the construction or verification of MPEG-2 transport stream. This article describes the theoretical principles and an original microelectronic hardware architecture of a conceptual decoder able to process a MPEG-2 DVB-T stream (T-STD) in real time. The proposed hardware architecture allows to continuously analysing the MPEG-2 video stream. The architecture has been modelled, validated and simulated by using the SystemC language in combination with real MPEG-2 DVB-T streams. It is composed of several modules allowing to model the various buffers of the video T-STD part. Real time errors flags are generated when the filling level of the buffers becomes illegal (overflow, underflow, no_empty_buffer, transfer delay). A VHDL model allows an implementation on the APEX20KE600 Altera FPGA circuit. The hardware implementation of the TSTD video part requires 4787 logical cells (LC) and 4.5 kB of memory capacity.
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Dates et versions

hal-03983687 , version 1 (11-02-2023)

Identifiants

  • HAL Id : hal-03983687 , version 1

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Michael Janiaut, Camel Tanougast, Christian Mannino, Hassan Rabah, Yves Berviller, et al.. Hardware implementation of a conceptual decoder for real time analysis of MPEG-2 DVB-T stream. 30 (31), pp.41, 2005. ⟨hal-03983687⟩
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