This paper presents a study on a few main challenges in GaN-based designs from component to board development level. Transistors in parallel in a switch are more critical in designing power cells due to the high sensitivity to parasitic components in both power and gate control circuits. Further, the changes in switching behaviour on the discrepancies in device parameters are yet to be realized. In this study, both experimental and simulation based approaches are used for the verification of parasitic effects. The large signal modeling with LTSpice simulation is used for the prediction of effect due to parametric variation of devices in parallel.