Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology - Archive ouverte HAL
Article Dans Une Revue Solid-State Electronics Année : 2022

Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology

Tristan Meunier

Résumé

This paper aims to benchmark the threshold voltage extraction at cryogenic temperature. It presents two DC andfor the first time one RF methods to extract the threshold voltage down to 4.2 K for channel lengths down to 28nm. Measurements are performed on CMOS transistors integrated in 28 nm Fully Depleted Silicon-On-Insulator(FDSOI). First, two methods based on DC measurement are explained: the constant-current and the second derivative technique. Besides, the gate-channel capacitance derivative method based on RF measurements is presented. Finally, we discuss and compare the advantages and limits of these different methods.

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Electronique
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hal-03974969 , version 1 (22-07-2024)

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Quentin Berlingard, Jose Lugo-Alvarez, Maryline Bawedin, Lauriane Contamin, Philippe Galy, et al.. Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology. Solid-State Electronics, 2022, 194, pp.108325. ⟨10.1016/j.sse.2022.108325⟩. ⟨hal-03974969⟩
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