Characterizing and quantifying the endurance of Resistive RAM devices is critical to assess their reliability for integration in electronic systems. This paper proposes a novel characterization methodology for rapid detection of RRAMs reliability issues during endurance tests. A test structure consisting of an array of non-addressable RRAM memory cells with parallel connection of all the memory elements is used for this purpose. The test structure fills the gap between isolated cells and circuit level endurance tests as it combines the test speed of an isolated cell while providing at the same time data from multiple devices. Endurance tests are conducted while monitoring RRAM electrical parameters of interest for each switching cycle. Experimental results show that most studies that claimed high endurance without capturing all switching cycles, or by considering an isolated cell, lead to an overestimation of the endurance. Finally, an endurance failures mitigation scheme based on RRAM current sensing in the RESET direction is presented to improve the endurance