CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibilities of reconfiguration that the FPGA component can offer. Here, we present a temporal hardware partitioning software, included in a design methodology that uses the reconfiguration possibilities of the FPGA for the SOC system design. This automated partitioning tool minimizes the number of cells needed to implement an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resource needs. It can also be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.