In this paper, we present a guideline to optimize the layout floorplan by minimizing the impact of on-wafer neighbouring structures in very high frequency (1 GHz to 220 GHz) on-wafer measurements of Si electronic devices. To present the guideline, a 3D electromagnetic (EM) simulation is carried out extensively using a realistic EM model of a commercial RF probe. First layout design dependent factors influencing the DUT characteristics are identified which are 1) way of positioning of the on-wafer structures w.r.t. DUT (e.g. in line or checkerboard pattern) and 2) the spacing between on-wafer structures and the DUT. Afterwards, a guideline to reduce the influence of on-wafer neighbours on the DUT characteristics is presented. The optimization of the layout floorplan with minimal on-wafer neighbours prior to their fabrication also permits to reduce the costs with respect to occupied Si area.