This paper presents the implementation of a new topology of 3D slow-wave transmission lines in CMOS technology. The proposed structure makes it possible to consider the design of compact circuits based on these 3D transmission lines presenting performances superior to the lumped elements approach (inductors and capacitors) for the Ka band, and in particular for 5G applications. The equivalent electrical model of the 3D structure, based on a physical analysis, is established, with excellent agreement with the measurement results. Then a filter based on parallel stubs is proposed in order to show the potentialities of the proposed 3D structure. The performances obtained are acceptable, with a power balance showing insertion loss potentially equal to 3 dB if the structure is matched, for a relative bandwidth of 22%. Development prospects concern the design of more complex filters but also of matching networks for LNAs or PAs.