Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells
Résumé
This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuitlevel, benchmarking TFET-against FinFET-based bitcells. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies at a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.
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