Communication Dans Un Congrès Année : 2022

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells

Résumé

This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuitlevel, benchmarking TFET-against FinFET-based bitcells. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies at a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.

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Dates et versions

hal-03812310 , version 1 (12-10-2022)

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Ariana Musello, Santiago Perez, Marco Villegas, Luis Miguel Procel, Ramiro Taco, et al.. Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. IEEE 13th Latin America Symposium on Circuits and System (LASCAS) 2022, Mar 2022, Puerto Varas, Chile. pp.1-4, ⟨10.1109/LASCAS53948.2022.9789086⟩. ⟨hal-03812310⟩

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