The race to reduce the size and improve power consumption in new transistor technologies has given rise to design trade-offs that are difficult to address with standard methodologies that require an iterative process. This paper proposes a design methodology based on the ACM model and look-up tables to quickly size a 28 nm FD-SOI RF LNA. The design incorporates different tuning knobs that can be useful for optimizing design constraints and, in particular, adapting the circuit performances at very low temperatures.