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Conference Papers Year : 2022

High-Level Synthesis for Hardware Implementation of Cryptography: Experience Feedback

Abstract

When implementing cryptographic elements in hardware, various types of languages and tools can be used. Hardware description languages (HDL), such as VHDL or Verilog, and related synthesis tools allow to master low level details but require important efforts. High-level synthesis (HLS) uses "higher" level languages, such as C, and specific tools to quickly produce circuits but with a much reduced control in implementation details. HDL and HLS methods lead to different trade-offs between training effort, design/debug/optimization times, obtained performances/costs. Neither HDL nor HLS support mathematical objects and operations required in crypto. Implementing protections against side channel attacks (observation and/or perturbation) can be tricky due to limited "links" between what designers can describe and some physical behavior. I will present examples on how we used HDL or HLS, the obtained results, effort evaluation and a few problems hardware designers face.
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Dates and versions

hal-03706731 , version 1 (05-07-2022)

Identifiers

  • HAL Id : hal-03706731 , version 1

Cite

Arnaud Tisserand. High-Level Synthesis for Hardware Implementation of Cryptography: Experience Feedback. Journées nationales du GDR Sécurité Informatique, Jun 2022, Paris, France. ⟨hal-03706731⟩
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