Coarse-grained reconfigurable architectures (CGRAs) are ideal computing devices as they provide both flexibility and performance. In this talk, we present a three-part approach that addresses architecture, compilation, and application to reach ultra-low power computing with CGRAs. First, we present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state-of-the-art approaches. We then present modifications applied at the application level to support transprecision computing, a variable size floating-point computing to adjust the precision of the results to the application needs. Finally, we present the SIMD and transprecision support in the CGRA. This global approach reaches an average of 10x energy improvement compared to a RISC-V based ultra-low-power digital signal processor.