From Semiconductor to Transistor-Level: Modeling, Simulation, and Layout Rendering Tools - Archive ouverte HAL
Poster De Conférence Année : 2022

From Semiconductor to Transistor-Level: Modeling, Simulation, and Layout Rendering Tools

Résumé

Research in semiconductor field has been overconfident in commercial tools, while open science urges for novel solutions based in open source tools. The MOSLab.jl is presented as a solution aiming to a fast, accurate and modular compact models to bridge the gap between semiconductor applied physics and microelectronics research in nanometer scaled technology. The icLayoutRender tool is demonstrated as a user-friendly solution to a GDSII transcription in a vectorial graph quality image saved as a pdf file.
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Dates et versions

hal-03690082 , version 1 (07-06-2022)

Identifiants

  • HAL Id : hal-03690082 , version 1

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João R. Raposo de O. Martins, Francisco Alves, Pietro Maris Ferreira. From Semiconductor to Transistor-Level: Modeling, Simulation, and Layout Rendering Tools. Colloque du GdR SOC2, Jun 2022, Strasbourg, France. ⟨hal-03690082⟩
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