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Article Dans Une Revue Microelectronics Reliability Année : 2003

Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies

Résumé

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO2 gate-oxide ranging from Tox= 3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the Tox thinning and the shrink of the gate-length with LG ranging from 0.25 to 0.1μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the Tox and LG margin. It is shown that the interface trap generation (ΔNit) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (ΔL) with the LG reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.

Dates et versions

hal-03667780 , version 1 (13-05-2022)

Identifiants

Citer

Alain Bravaix, C. Trapes, D. Goguenheim, N. Revil, E. Vincent. Carrier injection efficiency for the reliability study of 3.5–1.2 nm thick gate-oxide CMOS technologies. Microelectronics Reliability, 2003, Microelectronics Reliability, 43 (8), pp.1241-1246. ⟨10.1016/S0026-2714(03)00178-1⟩. ⟨hal-03667780⟩
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