<?xml version="1.0" encoding="utf-8"?>
<TEI xmlns="http://www.tei-c.org/ns/1.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:hal="http://hal.archives-ouvertes.fr/" xmlns:gml="http://www.opengis.net/gml/3.3/" xmlns:gmlce="http://www.opengis.net/gml/3.3/ce" version="1.1" xsi:schemaLocation="http://www.tei-c.org/ns/1.0 http://api.archives-ouvertes.fr/documents/aofr-sword.xsd">
  <teiHeader>
    <fileDesc>
      <titleStmt>
        <title>HAL TEI export of hal-03662244</title>
      </titleStmt>
      <publicationStmt>
        <distributor>CCSD</distributor>
        <availability status="restricted">
          <licence target="https://creativecommons.org/publicdomain/zero/1.0/">CC0 1.0 - Universal</licence>
        </availability>
        <date when="2026-05-11T06:35:59+02:00"/>
      </publicationStmt>
      <sourceDesc>
        <p part="N">HAL API Platform</p>
      </sourceDesc>
    </fileDesc>
  </teiHeader>
  <text>
    <body>
      <listBibl>
        <biblFull>
          <titleStmt>
            <title xml:lang="en">A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits</title>
            <author role="aut">
              <persName>
                <forename type="first">Yoan</forename>
                <surname>Decoudu</surname>
              </persName>
              <idno type="halauthorid">1604213-0</idno>
              <affiliation ref="#struct-1043047"/>
            </author>
            <author role="aut">
              <persName>
                <forename type="first">Katell</forename>
                <surname>Morin-Allory</surname>
              </persName>
              <email type="md5">34e9879ba0d9772b4ada5f8636f65d4f</email>
              <email type="domain">univ-grenoble-alpes.fr</email>
              <idno type="idhal" notation="string">katell-morin-allory</idno>
              <idno type="idhal" notation="numeric">735899</idno>
              <idno type="halauthorid" notation="string">38434-735899</idno>
              <affiliation ref="#struct-1043047"/>
            </author>
            <author role="aut">
              <persName>
                <forename type="first">Laurent</forename>
                <surname>Fesquet</surname>
              </persName>
              <email type="md5">2647878023e5c6e45e24b115e329551f</email>
              <email type="domain">univ-grenoble-alpes.fr</email>
              <idno type="idhal" notation="string">laurent-fesquet</idno>
              <idno type="idhal" notation="numeric">14246</idno>
              <idno type="halauthorid" notation="string">35057-14246</idno>
              <idno type="IDREF">https://www.idref.fr/081162073</idno>
              <idno type="ORCID">https://orcid.org/0000-0002-6045-8510</idno>
              <affiliation ref="#struct-1043047"/>
            </author>
            <editor role="depositor">
              <persName>
                <forename>Laurence</forename>
                <surname>BEN TITO</surname>
              </persName>
              <email type="md5">19a1abf4f2fb18274de189b7c316c0b3</email>
              <email type="domain">univ-grenoble-alpes.fr</email>
            </editor>
          </titleStmt>
          <editionStmt>
            <edition n="v1" type="current">
              <date type="whenSubmitted">2022-05-09 11:11:49</date>
              <date type="whenModified">2026-03-26 11:46:02</date>
              <date type="whenReleased">2022-05-19 13:54:06</date>
              <date type="whenProduced">2021-10-04</date>
              <date type="whenEndEmbargoed">2022-05-09</date>
              <ref type="file" target="https://hal.science/hal-03662244v1/document">
                <date notBefore="2022-05-09"/>
              </ref>
              <ref type="file" subtype="author" n="1" target="https://hal.science/hal-03662244v1/file/paper_45.pdf" id="file-3662247-3198004">
                <date notBefore="2022-05-09"/>
              </ref>
            </edition>
            <respStmt>
              <resp>contributor</resp>
              <name key="542059">
                <persName>
                  <forename>Laurence</forename>
                  <surname>BEN TITO</surname>
                </persName>
                <email type="md5">19a1abf4f2fb18274de189b7c316c0b3</email>
                <email type="domain">univ-grenoble-alpes.fr</email>
              </name>
            </respStmt>
          </editionStmt>
          <publicationStmt>
            <distributor>CCSD</distributor>
            <idno type="halId">hal-03662244</idno>
            <idno type="halUri">https://hal.science/hal-03662244</idno>
            <idno type="halBibtex">decoudu:hal-03662244</idno>
            <idno type="halRefHtml">&lt;i&gt;29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021)&lt;/i&gt;, Oct 2021, Singapore, Singapore. &lt;a target="_blank" href="https://dx.doi.org/10.1109/VLSI-SoC53125.2021.9606977"&gt;&amp;#x27E8;10.1109/VLSI-SoC53125.2021.9606977&amp;#x27E9;&lt;/a&gt;</idno>
            <idno type="halRef">29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021), Oct 2021, Singapore, Singapore. &amp;#x27E8;10.1109/VLSI-SoC53125.2021.9606977&amp;#x27E9;</idno>
            <availability status="restricted">
              <licence target="https://creativecommons.org/licenses/by-nc/4.0/">CC BY-NC 4.0 - Attribution - Non-commercial use<ref corresp="#file-3662247-3198004"/></licence>
            </availability>
          </publicationStmt>
          <seriesStmt>
            <idno type="stamp" n="UGA">HAL Grenoble Alpes</idno>
            <idno type="stamp" n="CNRS">CNRS - Centre national de la recherche scientifique</idno>
            <idno type="stamp" n="INPG">Institut polytechnique de Grenoble</idno>
            <idno type="stamp" n="TIMA">Techniques of Informatics and Microelectronics for integrated systems Architecture</idno>
            <idno type="stamp" n="UGA-EPE">Université Grenoble Alpes [2020-*]</idno>
            <idno type="stamp" n="TEST-UGA">TEST-UGA</idno>
          </seriesStmt>
          <notesStmt>
            <note type="audience" n="2">International</note>
            <note type="invited" n="0">No</note>
            <note type="popular" n="0">No</note>
            <note type="peer" n="1">Yes</note>
            <note type="proceedings" n="0">No</note>
          </notesStmt>
          <sourceDesc>
            <biblStruct>
              <analytic>
                <title xml:lang="en">A High-Level Design Flow for Locally Body-Biased Asynchronous Circuits</title>
                <author role="aut">
                  <persName>
                    <forename type="first">Yoan</forename>
                    <surname>Decoudu</surname>
                  </persName>
                  <idno type="halauthorid">1604213-0</idno>
                  <affiliation ref="#struct-1043047"/>
                </author>
                <author role="aut">
                  <persName>
                    <forename type="first">Katell</forename>
                    <surname>Morin-Allory</surname>
                  </persName>
                  <email type="md5">34e9879ba0d9772b4ada5f8636f65d4f</email>
                  <email type="domain">univ-grenoble-alpes.fr</email>
                  <idno type="idhal" notation="string">katell-morin-allory</idno>
                  <idno type="idhal" notation="numeric">735899</idno>
                  <idno type="halauthorid" notation="string">38434-735899</idno>
                  <affiliation ref="#struct-1043047"/>
                </author>
                <author role="aut">
                  <persName>
                    <forename type="first">Laurent</forename>
                    <surname>Fesquet</surname>
                  </persName>
                  <email type="md5">2647878023e5c6e45e24b115e329551f</email>
                  <email type="domain">univ-grenoble-alpes.fr</email>
                  <idno type="idhal" notation="string">laurent-fesquet</idno>
                  <idno type="idhal" notation="numeric">14246</idno>
                  <idno type="halauthorid" notation="string">35057-14246</idno>
                  <idno type="IDREF">https://www.idref.fr/081162073</idno>
                  <idno type="ORCID">https://orcid.org/0000-0002-6045-8510</idno>
                  <affiliation ref="#struct-1043047"/>
                </author>
              </analytic>
              <monogr>
                <meeting>
                  <title>29th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2021)</title>
                  <date type="start">2021-10-04</date>
                  <date type="end">2021-10-08</date>
                  <settlement>Singapore</settlement>
                  <country key="SG">Singapore</country>
                </meeting>
                <imprint>
                  <publisher>IFIP</publisher>
                </imprint>
              </monogr>
              <idno type="doi">10.1109/VLSI-SoC53125.2021.9606977</idno>
              <ref type="publisher">IFIPLink</ref>
            </biblStruct>
          </sourceDesc>
          <profileDesc>
            <langUsage>
              <language ident="en">English</language>
            </langUsage>
            <textClass>
              <keywords scheme="author">
                <term xml:lang="en">power management</term>
                <term xml:lang="en">high-level synthesis</term>
                <term xml:lang="en">fine-grain body biasing</term>
                <term xml:lang="en">FDSOI</term>
                <term xml:lang="en">bundled-data circuit</term>
              </keywords>
              <classCode scheme="classification">PACS 85.42</classCode>
              <classCode scheme="halDomain" n="spi.nano">Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics</classCode>
              <classCode scheme="halTypology" n="COMM">Conference papers</classCode>
              <classCode scheme="halOldTypology" n="COMM">Conference papers</classCode>
              <classCode scheme="halTreeTypology" n="COMM">Conference papers</classCode>
            </textClass>
            <abstract xml:lang="en">
              <p>&lt;p&gt;Fully Depleted Silicon on Insulator (FDSOI) technologies offer new possibilities for power &amp;nbsp;management, especially with dynamic body biasing. Traditional strategies are based on a large body bias generator, which drives the IP back-gates thanks to a dedicated and often complex power management system. As asynchronous circuits use local synchronizations with handshake components, which activate only the processing parts, it is possible to take advantage of these handshake signals to implement a simple and fine-grain body biasing strategy. Instead of driving IPs with a large body bias generator, we use tiny distributed generators, locally activating small body bias regions when the circuit is processing data. These latter are based on level-shifters and implemented as standard cells. Thus, we propose a high-level design flow associating asynchronous circuits and a local body biasing strategy, which does not require complex body bias management. Indeed, the local handshake signals directly control our dedicated body bias generators. Moreover, Place and Route operations are facilitated by the use of standard cell generators. The simulations show the flow efficiency, a finer grain body biasing and a significant power reduction.&lt;/p&gt;</p>
            </abstract>
          </profileDesc>
        </biblFull>
      </listBibl>
    </body>
    <back>
      <listOrg type="structures">
        <org type="researchteam" xml:id="struct-1043047" status="VALID">
          <orgName>Circuits, Devices and System Integration</orgName>
          <orgName type="acronym">TIMA-CDSI</orgName>
          <date type="start">2020-01-01</date>
          <desc>
            <address>
              <addrLine>Laboratoire TIMA, 46, avenue Félix Viallet - 38031 GRENOBLE Cedex</addrLine>
              <country key="FR"/>
            </address>
            <ref type="url">http://tima.univ-grenoble-alpes.fr/tima/fr/cdsi/cdsioverview.html</ref>
          </desc>
          <listRelation>
            <relation active="#struct-1043043" type="direct"/>
            <relation name="UMR5159" active="#struct-441569" type="indirect"/>
            <relation active="#struct-1042703" type="indirect"/>
            <relation active="#struct-1043329" type="indirect"/>
          </listRelation>
        </org>
        <org type="laboratory" xml:id="struct-1043043" status="VALID">
          <idno type="IdRef">02901364X</idno>
          <idno type="ISNI">0000 0001 2337 0176</idno>
          <idno type="RNSR">200311834E</idno>
          <idno type="ROR">https://ror.org/000063q30</idno>
          <orgName>Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés</orgName>
          <orgName type="acronym">TIMA</orgName>
          <date type="start">2020-01-01</date>
          <desc>
            <address>
              <addrLine>46 avenue Félix Viallet38031 GRENOBLE Cedex 1</addrLine>
              <country key="FR"/>
            </address>
            <ref type="url">http://tima.univ-grenoble-alpes.fr/</ref>
          </desc>
          <listRelation>
            <relation name="UMR5159" active="#struct-441569" type="direct"/>
            <relation active="#struct-1042703" type="direct"/>
            <relation active="#struct-1043329" type="direct"/>
          </listRelation>
        </org>
        <org type="regroupinstitution" xml:id="struct-441569" status="VALID">
          <idno type="IdRef">02636817X</idno>
          <idno type="ISNI">0000000122597504</idno>
          <idno type="ROR">https://ror.org/02feahw73</idno>
          <orgName>Centre National de la Recherche Scientifique</orgName>
          <orgName type="acronym">CNRS</orgName>
          <date type="start">1939-10-19</date>
          <desc>
            <address>
              <country key="FR"/>
            </address>
            <ref type="url">https://www.cnrs.fr/</ref>
          </desc>
        </org>
        <org type="regroupinstitution" xml:id="struct-1042703" status="VALID">
          <idno type="IdRef">240648315</idno>
          <idno type="ROR">https://ror.org/02rx3b187</idno>
          <orgName>Université Grenoble Alpes</orgName>
          <orgName type="acronym">UGA</orgName>
          <date type="start">2020-01-01</date>
          <desc>
            <address>
              <addrLine>Adresse CS 40700 - 38058 Grenoble cedex</addrLine>
              <country key="FR"/>
            </address>
            <ref type="url">http://www.univ-grenoble-alpes.fr</ref>
          </desc>
        </org>
        <org type="institution" xml:id="struct-1043329" status="VALID">
          <idno type="IdRef">026388804</idno>
          <idno type="ROR">https://ror.org/05sbt2524</idno>
          <orgName>Institut polytechnique de Grenoble - Grenoble Institute of Technology</orgName>
          <orgName type="acronym">Grenoble INP</orgName>
          <date type="start">2020-01-01</date>
          <desc>
            <address>
              <addrLine>46 avenue Félix Viallet 38031 Grenoble Cedex 1</addrLine>
              <country key="FR"/>
            </address>
            <ref type="url">http://www.grenoble-inp.fr/</ref>
          </desc>
          <listRelation>
            <relation active="#struct-1042703" type="direct"/>
          </listRelation>
        </org>
      </listOrg>
    </back>
  </text>
</TEI>