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Communication Dans Un Congrès Année : 2007

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation:

Résumé

Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrating the capabilities of the methodology as well highlighting the impacts of the two degradation modes.
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hal-03660397 , version 1 (05-05-2022)

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  • HAL Id : hal-03660397 , version 1

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Chittoor Parthasarathy, Alain Bravaix, Chloé Guérin, Mickael Denais, Vincent Huard. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation:: 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings. 17th International Workshop, PATMOS 2007,, Sep 2007, Goteborg Sweden, France. pp.191-200. ⟨hal-03660397⟩
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