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Article Dans Une Revue Solid-State Electronics Année : 2022

Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

D. Issartel
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R. Cellier
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D. Golanski
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A. Cathelin
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Résumé

This article presents a study of Single Photon Avalanche Diodes (SPAD) implemented in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) CMOS technology based on transient TCAD simulations and Dark Count Rate (DCR) measurements. The integration of SPAD in this technology is currently being studied. This work allows for a better understanding of the mechanism behind the quite high DCR measured at relative low excess bias voltages with the initial FD-SOI SPAD design (≈500 Hz/µm 2 at 5% excess bias voltage). In this study, a TCAD transient simulation methodology is introduced to better understand SPAD behavior during the avalanche process. TCAD simulations revealed that Shallow Trench Isolation (STI) structures within the active area have a negative effect on avalanche quenching, because of slower carrier evacuation with possible occurrence of secondary avalanches in series. Based on this analysis and on previous optimization works, we propose a new architecture of the FD-SOI SPAD combining several modifications to achieve a lower DCR (≈20 Hz/µm 2 at 5% excess bias voltage measured with passive quenching).
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Dates et versions

hal-03651521 , version 1 (25-04-2022)

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Citer

D. Issartel, S. Gao, P. Pittet, R. Cellier, D. Golanski, et al.. Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR. Solid-State Electronics, 2022, 191, pp.108297. ⟨10.1016/j.sse.2022.108297⟩. ⟨hal-03651521⟩
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