Track finding based on Associative Memories for Level-1 triggering in HL-LHC experiments
Résumé
The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <; 1MHz). A custom real-time system will be needed to extract the track information within the latency constraints (<;10usec). We developed the prototype of the building block of this system, the Pattern Recognition Mezzanine (PRM) that combines the power of both Associative Memory custom ASICs and modern FPGA devices. The architecture and the functionalities of the PRM are described here.
Mots clés
pattern recognition mezzanine
PRM
application specific integrated circuit
ASIC
field programmable gate array
CERN LHC Coll
track data analysis
integrated circuit
trigger
efficiency
Field programmable gate arrays
Associative memory
Clocks
Bit error rate
Pattern recognition
Connectors
Fitting
real-time systems
application specific integrated circuits
field programmable gate arrays
particle accelerators
pattern recognition
physics computing
FPGA
associative memory
AM
level-1 triggering
high luminosity upgrade of the CERN Large Hadron Collider
HL-LHC
real-time system
track information extraction