Recently adopted in the New Radio (NR) standard for 5G control channel, polar codes represent one of the latest additions to the family of forward error correction (FEC) codes. However, the stringent requirements introduced by the 5G standard in terms of block length and code rate flexibility, together with low end-to-end latency and high error correction performance, pose a major challenge for their hardware implementation. In this context, we study the impact of main code and decoder design parameters on the latency and the hardware complexity of semi-parallel decoding architectures. Detailed analytical and logic synthesis results are provided and compared for a large range of values in order to constitute a reference for the implementation of flexible, yet efficient FEC decoders for polar codes.