Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering - Archive ouverte HAL
Journal Articles Nano Letters Year : 2024

Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering

Abstract

Vertical gate-all-around (V-GAA) represents the ultimate configuration in the forthcoming transistor industry, but it still encounters challenges in the semiconductor community. This paper introduces, for thefirst time, a dual-input logic gate circuit achieved using 3D vertical transistorswith nanoscale sub-20-nm GAA, employing a novel technique for creating contacts and patterning metallic lines at the bottom level without the conventional lift-off process. This involves a two-step oxidation process:patterning the first field oxide to form bottom metal lines and then creating the gate oxide layer on nanowires (NWs), followed by selective removal from the top and bottom of the nanostructures. VGAA-NW transistors, fabricated using the lift-off-free approach, exhibit improved yield and reduced access resistance, leading to an enhanced drive current while maintaining good immunity against short-channel effects. Finally, elementary two-input logic gates within a single cell, using VNW transistors, demonstrate novel possibilities in advanced logic circuitry design and routing options in 3D.
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Origin Publication funded by an institution

Dates and versions

hal-03600982 , version 1 (09-07-2024)

Identifiers

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Abhishek Kumar, Jonas Müller, Sylvain Pelloquin, Aurélie Lecestre, Guilhem Larrieu. Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering. Nano Letters, 2024, 24 (26), pp.7825-7832. ⟨10.1021/acs.nanolett.3c04180⟩. ⟨hal-03600982⟩
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