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Communication Dans Un Congrès Année : 2021

Circuit-level evaluation of a new zero-cost transistor in a embedded non-volatile memory CMOS technology

Résumé

This work presents a new transistor architecture developed by reusing already existing fabrication process steps in an embedded non-volatile memory (eNVM) CMOS technology. The proposed transistor is derived from an existing high-voltage transistor and is free in terms of photomasks and process steps, making it ideal for low-cost products. The new transistor is fabricated then electrically characterized, showing good analog performances. A SPICE (Simulation Program with Integrated Circuit Emphasis) model of the new device is developed to assess its circuit-level performances through electrical circuit simulation. The in-circuit performances of the new device are evaluated based on different ring oscillator circuits. A comparison with the existing high-voltage transistor is carried out considering performance parameters such as the oscillating frequency to demonstrate the appeal of our new transistor.
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Dates et versions

hal-03502361 , version 1 (24-12-2021)

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Citer

Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, et al.. Circuit-level evaluation of a new zero-cost transistor in a embedded non-volatile memory CMOS technology. 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-5, ⟨10.1109/DTIS53253.2021.9505137⟩. ⟨hal-03502361⟩
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