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Communication Dans Un Congrès Année : 2021

Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology

Romeric Gay
  • Fonction : Auteur
  • PersonId : 1121279
Vincenzo Della Marca
Stephan Niel
  • Fonction : Auteur
  • PersonId : 1121281
Abderrezak Marzaki
  • Fonction : Auteur
  • PersonId : 1121282

Résumé

This paper addresses the design and characterization of different architectures of novels highdensity multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.
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Dates et versions

hal-03502360 , version 1 (24-12-2021)

Identifiants

Citer

Romeric Gay, Vincenzo Della Marca, Hassen Aziza, Arnaud Regnier, Stephan Niel, et al.. Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology. 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Jun 2021, Montpellier, France. pp.1-4, ⟨10.1109/DTIS53253.2021.9505093⟩. ⟨hal-03502360⟩
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