Back gate impact on the noise performances of 22FDX fully-depleted SOI CMOS
Ousmane Magatte Kane
(1, 2)
,
Luca Lucci
(1)
,
Pascal Scheiblin
(1)
,
Thierry Poiroux
(1)
,
Jean-Charles Barbé
(1)
,
Francois Danneville
(3, 2)
Thierry Poiroux
- Fonction : Auteur
- PersonId : 780274
- ORCID : 0000-0002-9641-9652
Francois Danneville
- Fonction : Auteur
- PersonId : 747124
- IdHAL : francois-danneville
- ORCID : 0000-0002-4725-0010
Résumé
Ultra-Thin-Body and Back-oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) MOSFETs are the most recent and advanced Silicon-On-Insulator (SOI) architecture proposed to overcome the down-scaling limitations of traditional bulk devices. The UTBB-FDSOI architecture has already been proved very attractive for RF-mmW circuits thanks to the excellent reported RF figure of merits (FOMs).In this article, we report on an experimental investigation of the back gate biasing impact on the high-frequency (HF) noise performances of an advanced 22 nm UTBB-FDSOI technology developed by GLOBALFOUNDRIES. For the lower gate voltages, the back gate biasing was shown to decrease by one third the equivalent noise resistance (Rn). Moreover, a 3 dB increase for the associated gain (Ga) was achieved at Vg=0.3V. A relaxed contacted-poly-pitch was also shown to decrease Rn by 11%.
Domaines
Sciences de l'ingénieur [physics]Format du dépôt | Notice |
---|---|
Type de dépôt | Communication dans un congrès |
Titre |
en
Back gate impact on the noise performances of 22FDX fully-depleted SOI CMOS
|
Résumé |
en
Ultra-Thin-Body and Back-oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) MOSFETs are the most recent and advanced Silicon-On-Insulator (SOI) architecture proposed to overcome the down-scaling limitations of traditional bulk devices. The UTBB-FDSOI architecture has already been proved very attractive for RF-mmW circuits thanks to the excellent reported RF figure of merits (FOMs).In this article, we report on an experimental investigation of the back gate biasing impact on the high-frequency (HF) noise performances of an advanced 22 nm UTBB-FDSOI technology developed by GLOBALFOUNDRIES. For the lower gate voltages, the back gate biasing was shown to decrease by one third the equivalent noise resistance (Rn). Moreover, a 3 dB increase for the associated gain (Ga) was achieved at Vg=0.3V. A relaxed contacted-poly-pitch was also shown to decrease Rn by 11%.
|
Auteur(s) |
Ousmane Magatte Kane
1, 2
, Luca Lucci
1
, Pascal Scheiblin
1
, Thierry Poiroux
1
, Jean-Charles Barbé
1
, Francois Danneville
3, 2
1
CEA-LETI -
Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
( 40214 )
- MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9
- France
2
IEMN -
Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520
( 1066983 )
- [Univ. Lille, CNRS, Centrale Lille Institut, Junia, Univ. Polytechnique Hauts-de-France] ––
Laboratoire Central – Cité Scientifique – Avenue Poincaré – CS 60069 – 59652 VILLENEUVE D’ASCQ CEDEX
- France
3
ANODE - IEMN -
Advanced NanOmeter DEvices - IEMN
( 1067380 )
- Groupe ANODE (Composants et dispositifs nanométriques) - IEMN LCI - Avenue Poincaré - CS 60069
59650 Villeneuve d'Ascq
- France
|
Langue du document |
Anglais
|
Vulgarisation |
Non
|
Comité de lecture |
Oui
|
Invité |
Non
|
Audience |
Internationale
|
Actes |
Oui
|
Date de publication |
2021
|
Numéro |
ISBN 978-1-7281-7040-4
|
Page/Identifiant |
81-84, https://ieeexplore.ieee.org/abstract/document/9337333
|
Titre du congrès |
15th European Microwave Integrated Circuits Conference, EuMIC 2020
|
Date début congrès |
2021-01-11
|
Date fin congrès |
2021-01-12
|
Ville |
Utrecht
|
Pays |
Pays-Bas
|
Domaine(s) |
|
Éditeur commercial |
|
Référence interne |
|
Mots-clés |
en
CMOS, FDSOI, back gate, 22FDX, noise measurement, millimeter wave
|
UT key WOS | 000654861200021 |
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