This paper describes the implementation of the CMOS 20 nm technology of a High Performance Bulk Planar 20nm CMOS Technology proposed by the Joint Development Alliance (JDA) in Microwind38. Power, performance and area (PPA) gains related to the 20 nm technology are illustrated, and new concepts such as design for manufacturing, double-patterning, replacement metal gate process are described. The performances of a ring oscillator layout and a 6-transistor RAM memory layout are also analyzed.