Introducing 65 nm technology in Microwind3
Résumé
This paper describes the improvements related to the CMOS 65 nm technologies and the implementation of this technology in Microwind3. The main novelties related to the 65 nm technology such as enhanced strained silicon, process options and low-K dielectrics are described. The performances of a ring oscillator and the 6-transistor static memory layout are also analyzed.
| Origine | Fichiers produits par l'(les) auteur(s) |
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