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Autre Publication Scientifique Année : 2011

Introducing 65 nm technology in Microwind3

Résumé

This paper describes the improvements related to the CMOS 65 nm technologies and the implementation of this technology in Microwind3. The main novelties related to the 65 nm technology such as enhanced strained silicon, process options and low-K dielectrics are described. The performances of a ring oscillator and the 6-transistor static memory layout are also analyzed.
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Dates et versions

hal-03324309 , version 1 (23-08-2021)

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  • HAL Id : hal-03324309 , version 1

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Etienne Sicard, Syed Mahfuzul Aziz. Introducing 65 nm technology in Microwind3. 2011. ⟨hal-03324309⟩
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