Power-efficient reliable register file for aggressive-environment applications
Résumé
In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors' results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.
Mots clés
reduced power budget
serious design challenge
embedded system manufacturers
embedded processors
aggressive environments
error hardening
critical element
processor pipeline
fault immune computing systems
authors propose
RF architecture
adjacent byte-level narrow-width values
integer registers
nonutilised bits
counterpart register
floating point critical bits
low power budget
normal operating conditions
highly aggressive operating conditions
floating point RF reliability enhancement techniques
adjacent register hardened RF
embedded systems
microprocessor chips
integrated circuit reliability
power aware computing
floating point arithmetic
reliability
flip-flops
power-efficient reliable register file
aggressive-environment applications
on-board data processing
Fichier principal
ALOUANI_Ishen_IET Computers Digital Tech _2019.pdf (3.53 Mo)
Télécharger le fichier
Origine | Fichiers éditeurs autorisés sur une archive ouverte |
---|---|
Licence |