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Article Dans Une Revue IEEE Transactions on Communications Année : 2021

Sign-Preserving Min-Sum Decoders

Résumé

This paper proposes a new finite precision iterative decoder for low-density parity-check (LDPC) codes. The proposed decoder, named Sign-Preserving Min-Sum (SP-MS), significantly improves the decoding performance compared to the classical Offset Min-Sum (OMS) decoder when messages are quantized on q = 2, 3, or 4 bits. The particularity of the SP-MS decoder is that messages cannot take the 0 value, and can fully benefit from the q bits of precision. The optimization of the SP-MS decoder is investigated in the asymptotic limit of the code length using density evolution (DE). Our study shows that 3-bit SP-MS decoders can achieve the same error-correcting performance as 5-bit OMS decoders, and 2-bit SP-MS decoders outperform 3-bit OMS decoders. The finite-length simulations confirm the conclusions of the DE analysis for several LDPC codes. Our SP-MS decoder shows a signal-to-noise ratio (SNR) gain up to 0.43 dB, with a memory/wire reduction of up to 40%, compared to the OMS decoder. Moreover, the SP-MS decoder converges faster and uses fewer iterations than the OMS decoder, with an improvement of up to 83.3% of the average decoding throughput. On an FPGA, the SP-MS decoder reduces resource utilization by up to 56% compared to the OMS decoder.
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Dates et versions

hal-03311512 , version 1 (01-08-2021)

Identifiants

  • HAL Id : hal-03311512 , version 1

Citer

F Cochachin, Emmanuel Boutillon, D Declercq. Sign-Preserving Min-Sum Decoders. IEEE Transactions on Communications, 2021, 69 (10), pp.6439-6454. ⟨hal-03311512⟩
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