Cascaded Smart Gate Drivers for Modular Multilevel Converters Control: A Decentralized Voltage Balancing Algorithm
Résumé
Recent Modular Multilevel Converter (MMC) topology allow drastic improvements in power electronic conversion such as higher energy quality, lower power semiconductors electrical stress, decreased Electro-Magnetic Interferences (EMI), and reduced switching losses. MMC is widely used in High Voltage Direct-Current (HVDC) transmissions, as it offers theoretically no voltage limit. However, its control electronic structure is not modular itself. Especially, the insulation voltage between the submodule gate drivers’ primaries and secondaries depends on the number of submodule. The converter voltage levels cannot be increased without designing again all gate driver isolations. To solve that issue, the novel concept of distributed galvanic insulation is introduced for multilevel converters. The submodule’s gate drivers are daisy chained, which naturally reduces the insulation voltage to the submodule capacitor voltage, regardless of the number of submodules. The MMC becomes truly modular as the number of submodule can be increased without impacting previous control electronic circuit. Such innovative control structure weakens the link between main control unit and gate drivers. This inherent structural problem can be solved through the use of Smart-Gate Drivers (SGD), as they are often equipped with fast and bidirectional communication channels, while highly increasing the converter reliability. The innovation proposed in that work is the involvement of smart gate drivers in the distributed galvanic insulation based MMC control and monitoring. First, the numerous benefits of smart gate drivers are discussed. Then, an innovative Voltage Balancing Algorithm directly integrated on the chained gate drivers is proposed and detailed. It features a tunable parameter, offering a trade-off between accurate voltage balancing and execution time. The proposed embedded algorithm features low execution time due to simultaneous voltage comparisons. Such algorithm is executed by the gate drivers themselves, relieving the main control unit in an original decentralized control scheme. A simulation model of a multi-megawatts three phase grid-tied MMC inverter is realized, allowing validation of the proposed algorithm. Matlab/Simulink logic blocs allows to simulate a typical CPLD/FPGA component, often embedded on smart gate drivers. The converter with proposed embedded algorithm is simulated in steady-state and during load impact. The controlled delay and slew-rate inferred by the algorithm does not disturb the converter behavior, allowing its conceptual validation.
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