High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node - Archive ouverte HAL Access content directly
Conference Papers Year : 2020

High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node

M. Gupta
  • Function : Correspondent author
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M. Perumkunnil
  • Function : Author
Kevin Garello
S. Rao
  • Function : Author
F. Yasin
  • Function : Author
G.S. Kar
  • Function : Author
A. Furnemont
  • Function : Author

Abstract

Spin Orbit Torque (SOT) magnetic random-access memory (MRAM) offers the possibility to realize ultra-highspeed Non-Volatile memory technology without endurance issues that plague its more mature counterpart, STT-MRAM, but at cost of density. Based on our SOT-MRAM technology data, we explore different bit-cell architectures through extensive Design Technology Co-optimization (DTCO) to evaluate the most pareto-optimum solutions for High-Density [HD] and High-Performance [HP] and we design full SOTMRAM macro for embedded domain. Our design-technology specifications projections show that using Resistance-Area (RA) product of 4 Ω.µm2, MTJ diameter of 32nm, SOT trackwidth of 35nm and SOT efficiency θSHE ≥1.4 enables: i) a HP SOT-MRAM macro with operating frequency (RD/WR) ≈ 1.05/0.71GHz at the 5nm process node and a 40% bit-cell area reduction compared to the 122 SRAM, ii) a HD SOT-MRAM macro with operating frequency (RD/WR) ≈ 1.1/0.45GHz and 37.5% area reduction compared to the 111 SRAM. Our analysis reveals that the bit line parasitic will be a limiting factor to SOT-MRAM performance at advanced nodes
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Dates and versions

hal-03239738 , version 1 (27-05-2021)

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M. Gupta, M. Perumkunnil, Kevin Garello, S. Rao, F. Yasin, et al.. High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node. 2020 IEEE International Electron Devices Meeting (IEDM), Dec 2020, San Francisco (virtuel), United States. pp.24.5.1-24.5.4, ⟨10.1109/IEDM13553.2020.9372068⟩. ⟨hal-03239738⟩
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