The degradation of Schottky Barrier Diodes (SBDs) with a Gated Edge Termination (GET) under on-state stress conditions is studied for a 650 V GaN-on-Si technology. Reliability metric techniques previously used in MOS-HEMTs are applied in this work due to a similar MIS gate stack architecture in GET-SBDs. Here, the density of traps is analyzed in GET structures where the dielectric is either Si 3 N 4 (nitride-based) or a stack of Al 2 O 3 /SiO 2 (oxide-based). Statistical analysis across two wafers indicates some systematic differences in turn-on voltage degradation depending on wafer location, likely caused by process-related variations. Under 1000 s stress time and ON-state voltage, the number of trapped charges in nitride-based dielectric devices keeps increasing. This suggests an ongoing dielectric degradation. On the other hand, Al 2 O 3 /SiO 2 dielectric devices with an Al-based interfacial layer (IL) exhibit less process-induced variability across the wafer along with a lower density of trapped charges compared with nitride-based dielectric diodes under the same stress conditions suggesting better reliability and process improvement.