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Communication Dans Un Congrès Année : 2021

Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers

Résumé

This paper presents the a design methodology for 112Gb/s PAM4 ADC-based receivers. The methodology is based on channel equalization to validate the specifications is proposed. A complete high-speed serial link in MATLAB Simulink was simulated. It is demonstrated the receiver is capable to equalize input data with channel losses close and up to 30dB at Nyquist Frequency. A combination of CTLE, long FFE taps with one-tap DFE presents as the best solution to cancel ISI. The resulting Bit Error Rate (BER) is within the specified range of 1×10–4 to 1×10-5.

Domaines

Electronique
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Dates et versions

hal-03042261 , version 1 (06-12-2020)

Identifiants

  • HAL Id : hal-03042261 , version 1

Citer

David Cordova, Wim Cops, Yann Deval, Francois Rivet, Herve Lapuyade, et al.. Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers. 12th IEEE Latin American Symposium on Circuits and Systems (LASCAS), Feb 2021, Arequipa, Peru. ⟨hal-03042261⟩
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