Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2021

Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX

Résumé

An offset voltage (VOS) calibration technique for dynamic comparators using body biasing is presented. The calibration uses a smart resettable successive approximation register (SR-SAR) algorithm to extract the offset voltage inside a fast and simple iterative loop, where the body bias of the comparator’s differential input pair is monotonically increased or decreased to counter balance the extracted offset voltage at each iteration. A study case using a strong ARM comparator implemented in 22nm FDSOI technology shows the advantages of using body biasing calibration to reduce σVOS by a factor of 12 while speeding-up the simulation time by 64 compared to the traditional linear approach.

Domaines

Electronique
Fichier non déposé

Dates et versions

hal-03042259 , version 1 (06-12-2020)

Identifiants

  • HAL Id : hal-03042259 , version 1

Citer

David Cordova, Wim Cops, Yann Deval, Francois Rivet, Herve Lapuyade, et al.. Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX. 12th IEEE Latin American Symposium on Circuits and Systems (LASCAS), Feb 2021, Arequipa, Peru. ⟨hal-03042259⟩
33 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More