Communication Dans Un Congrès Année : 2020

Efficient 8-bit matrix multiplication on Computational SRAM architecture

Résumé

This paper proposes a micro-kernel to efficiently compute 4x4 8-bit matrix multiplication on In-Memory Computing (IMC) Architectures with 128-bit word-lines. The proposed implementation requires simple instructions with vector-data computation and could be used as a basic block to implement General Matrix Multiplication (GEMM) on 128-bit word-lines IMC architectures, using 4x4 matrix partitioning. This micro-kernel would be beneficial to domains such as image processing and computer graphics.

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hal-02934838 , version 1 (09-09-2020)

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  • HAL Id : hal-02934838 , version 1

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Kévin Mambu, Henri-Pierre Charles, Maha Kooli. Efficient 8-bit matrix multiplication on Computational SRAM architecture. DATE 2020 ; Computing-in-Memory (CiM) Workshop, Mar 2020, Grenoble, France. ⟨hal-02934838⟩
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