Analysis of Energy-Delay-Product for a 3D Vertical Nanowire FET Technology for Logic Applications
Résumé
This document proposes a simplified analysis of the energy-delay-product (EDP) for a junction-less 3D vertical gate-all-around nanowire FET technology, with a physical channel length of 14nm, in comparison with the EDP of a baseline 7nm FinFET technology.
Origine | Fichiers produits par l'(les) auteur(s) |
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