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Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter

Abstract

This paper presents a functional design and modeling of a successive approximation analog to digital converter(SAR ADC). The SAR ADC is described in VHDL-AMS behavior models and transistor level circuit netlists using the 0.13μm technology and supply voltage equals to 1.2V. The system was simulated using a signal commercial simulator.
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Dates and versions

hal-02535544 , version 1 (07-04-2020)

Identifiers

  • HAL Id : hal-02535544 , version 1

Cite

Raouf Khalil, Mootaz Allam, Ramy Iskander, Marie-Minerve Louërat. Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter. Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Jun 2010, Paris, France. pp.1-2. ⟨hal-02535544⟩
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