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Conference Papers Year : 2020

Toward Secured IoT Devices: a Shuffled 8-Bit AES Hardware Implementation

Abstract

In this paper, we present a lightweight secured AES hardware implementation designed to further resist to Side Channel Attacks relying on Power Analysis. The proposed architecture is based on an 8-bit data-path, and the protection is provided by shuffling computations and memory locations. Our shuffling module is based on a permutation network controlled by a Random Number Generator and leads to the best compromise between security, area, and performances compared to state-of-the-art. Implementation results on a spartan-6 FPGA show that the proposed protection mechanisms impact the area and the timing performance of the unprotected design by factors of 1.58 and 0.35 respectively. Security evaluation based on simulation results shows that the proposed secure architecture resists to a regular CPA by revealing a unique key byte when attacking with up to 1 million traces while state-of-the-art shuffled designs requires only 50000 traces to retrieve the entire secret key. Considering an integrated CPA (also called windowing attack), the proposed architecture allows increasing up to ×300 the required number of traces (Measurements to Disclosure) to retrieve 40% of the key bytes and reveals no more than 9 key bytes when attacking with up to 1 million traces.
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Dates and versions

hal-02511667 , version 1 (25-02-2021)

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Ghita Harcha, Vianney Lapotre, Cyrille Chavet, Philippe Coussy. Toward Secured IoT Devices: a Shuffled 8-Bit AES Hardware Implementation. IEEE International Symposium on Circuits and Systems (ISCAS), Oct 2020, Seville, Spain. ⟨10.1109/ISCAS45731.2020.9180599⟩. ⟨hal-02511667⟩
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