This paper presents an ultra-high-throughput de-coder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one line of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N,K) = (144, 120) symbols over GF(64). The synthesis results on 28-nm technology show that the proposed architecture improves the throughput efficiency of the state of the art by a factor greater than 10. The architecture reaches a throughput above 10 Gb/s for SNR values greater than 5 dB. Compared to a 5G binary LDPC code of same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10 − 3. The proposed architecture reduces the required memory bandwidth by almost 50 % compared to a classical LDPC code. We also provide a detailed comparison with competitive state-of-the-art NB-LDPC decoder implementations in terms of performance, surface and decoding throughput are given.