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              <p>Due to the inherent features of the multilevel Flying Capacitor (FC) converter, the voltages in the capacitors are naturally balanced under phase-shifted pulse width modulation (PS-PWM) techniques. Nevertheless, under certain operation conditions the voltages in the capacitors vary between the commutation cells and an external balancer booster is required. This paper provides a methodology to properly design the balance booster for a FC converter with n-cells based on vectorized models. However, due to the trade-off between balancing speed and power losses, it is difficult to design a balance booster based on speed requirements, and checking loss constraints afterwards may result in a very long iterative process. Designing for losses and checking for speed is a much simpler process and this illustrated here for different types of balance boosters. Some simulations results obtained in PLECS R , are provided to enhance the benefits of the vectorized model for power electronic circuits, and the application to the design of balance boosters is presented.</p>
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