Lowering the Dark Count Rate of SPAD Implemented in CMOS FDSOI Technology
Résumé
This article presents an optimization study aiming at decreasing the Dark Count Rate (DCR) of Single Photon Avalanche Diodes implemented in CMOS Fully Depleted Silicon-On-Insulator technology presenting initially a low breakdown voltage and therefore an excess of band-to-band tunneling generation rate, leading to high DCR. It can nevertheless decrease by 5 decades with a single implant modification in the fabrication process.
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