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Conference Papers Year : 2019

RISC-V design using Free Open Source Software

Abstract

This tutorial aims to build a RISC-V processor using only free VLSI CAD tools with a symbolic technology approach (a refined Mead-Conway method as formerly used by MOSIS). The toolchain is currently organized as follow: A design description in VHDL language. Simulation with GHDL. Logical synthesis with Yosys. We use a frontend to convert VHDL into Verilog (from Alliance). Physical design (place & route) using Coriolis. DRC & LVS using Alliance. Timing analysis with Tas & Yagle. Symbolic to real translation (Alliance). Our first objective is to design a RISC-V for AMS 350nm node. The choice of symbolic technology is mainly made for three reasons: Node portability: From one symbolic layout, you may target multiple technologies. Community: Symbolic layout does not contain any NDA related information. As such it can freely be published and shared. Security.:With a published layout, everybody can check that the chip send back from the foundry is exactly what it should be (no hardware trojan).
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Dates and versions

hal-02316711 , version 1 (15-10-2019)

Identifiers

  • HAL Id : hal-02316711 , version 1

Cite

Jean-Paul Chaput, Marie-Minerve Louërat, Roselyne Chotin-Avot, Adrian Satin. RISC-V design using Free Open Source Software. the RISC-V Week, Oct 2019, Paris, France. ⟨hal-02316711⟩
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