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Conference Papers Year : 2019

Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs

Abstract

A common problem when developing signal processing applications is to expose and exploit parallelism in order to improve both throughput and latency. Many programming paradigms and models have been introduced to serve this purpose, such as the Synchronous DataFlow (SDF) Model of Computation (MoC). SDF is used especially to model signal processing applications. However, the main difficulty when using SDF is to choose an appropriate granularity of the application representation , for example when translating imperative functions into SDF actors. In this paper, we propose a method to model the parallelism of perfectly nested for loops with any bounds and explicit parallelism, using SDF. This method makes it possible to easily adapt the granularity of the expressed parallelism, thanks to the introduced concept of SDF iterators. The usage of SDF iterators is then demonstrated on the Scale Invariant Feature Transform (SIFT) image processing application.
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Dates and versions

hal-02267487 , version 1 (19-08-2019)
hal-02267487 , version 2 (04-09-2019)

Identifiers

Cite

Alexandre Honorat, Karol Desnos, Maxime Pelcat, Jean-François Nezan. Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs. Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩. ⟨hal-02267487v2⟩
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