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Communication Dans Un Congrès Année : 2008

From application to ASIP-based FPGA prototype : a case study on turbo decoding

Olivier Muller
Michel Jezequel

Résumé

ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based implementation of a high throughput flexible turbo decoder. It introduces turbo decoding application and proposes an Application-Specific Instruction-set Processor with SIMD architecture, a specialized and extensible instruction-set, and 6-stages pipeline control. The proposed ASIP is developed in LISA language and generated automatically using the Processor Designer framework from CoWare. The paper illustrates how the automatic generated RTL code of the ASIP can be adapted for a rapid prototyping on PPGA reconfigurable logic and memory resources. Tor a Xilinx Virtex-II Pro PPGA, a single ASIP prototype occupies 68% of PPGA resources and achieves a 6.3 Mbit/s throughput when decoding a double binary turbo code with 5 iterations.

Dates et versions

hal-02194910 , version 1 (26-07-2019)

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Olivier Muller, Amer Baghdadi, Michel Jezequel. From application to ASIP-based FPGA prototype : a case study on turbo decoding. RSP'2008 : the 19th IEEE/IFIP international symposium on rapid system prototyping, Jun 2008, Monterey, United States. pp.128 - 134, ⟨10.1109/RSP.2008.16⟩. ⟨hal-02194910⟩
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