This paper deals with the design of on-chip communication network for multiprocessor convolutional turbo decoding. It proposes a new on-chip network based on the de Bruijn graph and compares its performances with two previously proposed networks based on Butterfly and Bene¿ topologies. The main characteristics of the de Bruijn network -including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique- allow it to efficiently support the communication intensive nature of the turbo decoding application. The paper describes the hardware implementation of the three networks; including routers, network interfaces, routing algorithms, and the packet format. The obtained results for a 16-processor de Bruijn network with an ST CMOS 90 nm technology demonstrate a major aggregate bandwidth of 534 Gbps with a small area of 0.704 mm2. Besides, the flexibility and the scalability of this on-chip communication network enable it to be used efficiently for any convolutional turbo code.